Packaging of semiconductor devices has lead to the implementation of various techniques to effect electrical connections to the semiconductor devices as well as to effect paths to dissipate heat. One known technique to provide electrical connections includes selectively bonding wires to the semiconductor device. This technique referred to as ‘wire-bonding’ has certain drawbacks. For example, wire bonds add parasitic inductance, which can impact the performance of the semiconductor device especially at comparatively high frequency operation. In addition, wire bonds do not efficiently dissipate heat away from the semiconductor device. These and other drawbacks to wire-bonding have led to the implementation of so-called pillars as an alternate method of effecting electrical and thermal connections to semiconductor devices.
FIG. 1 shows a known semiconductor structure 100. The semiconductor structure 100 comprises a substrate 101. The substrate 101 is GaAs and includes a collector layer 102 formed therein by known methods. A base layer 103 is provided over the collector layer 102, and an emitter layer 104 is provided over the collector layer 102 to provide a heterojunction bipolar transistor (HBT).
Contacts 105 are made to the base layer 103 and the collector layer 102. A first metal layer 106 is provided on the contacts 105 and the emitter layer 104. A second metal layer 107 is provided on the first metal layer 106. The first metal layer 106 and the second metal layer 107 are used for routing signals to and from the HBT. A third metal layer 108 is provided on the second metal layer 107. The third metal layer 108 provides a planar surface for attachment of a pillar 109 thereover. The pillar 109 provides a thermal dissipation path and electrical ground through the third metal layer 108. A layer 110 of benzocyclobutene (BCB) or polyimide is provided beneath the third metal layer 108 and provides a planar surface on which the third metal layer 108 is formed.
Because each successive metal layer must fit within the ‘footprint’ of the last metal layer, the feature size of each successive metal layer must be smaller than the feature size of the previous metal layer. For example, second metal layer 107 has narrower line-widths than the first metal layer 106. However, with each successive metal layer, photolithographic resolution is reduced. This reduction in photolithographic resolution results in an overall increase in the feature size of each successive metal layer, and ultimately an increase in the size of the die of the semiconductor structure. Moreover, in the semiconductor structure 100, the upper-most metal layer (third metal layer 108) is comparatively thick, but cannot be used for signal routing under the pillar 109. Thus, the current-handling capability of the upper-most metal layer is not efficiently utilized in the semiconductor structure 100.
There is a need, therefore, for a semiconductor structure that supports a minimum number of metal layers to be used while overcoming at least the shortcomings of known semiconductor interconnect structures discussed above.